1. Field of the Invention
This invention pertains in general to digital signal processing and in particular to data structures for storing portions of the digital video signal during processing.
2. Description of Background Art
Modern computer systems have graphics processing subsystems capable of processing video signals as well as graphics commands. Video signals contain many frames of video data and are typically generated by devices like television tuners and Motion Pictures Expert Group (MPEG) decoders. Graphics commands, in contrast, are data specifying drawing instructions and typically arrive from the central processing unit of the computer system.
Video signals undergo a large amount of processing before display. First, the video signals are converted from either the NTSC or PAL formats into the format used by the video processor. Then, the video signals are processed to improve the picture quality. For example, television signals are interlaced and typically of a much lower resolution than that supported by the computer system display and must be de-interlaced by replicating vertical lines to make the picture appear to keep a normal aspect ratio on the display. Complex digital signal processing (DSP) techniques are used to replicate lines without generating undesirable display artifacts.
In order to perform this DSP, a graphics processing subsystem of a computer system usually has an engine dedicated to video DSP (VDSP). The engine has a number of sub-units, with each sub-unit performing one or more of the various VDSP functions. Many of the sub-units use discrete line memories, each holding a line of video data, and discrete field memories, each holding one-half of a frame of video data.
Implementing a VDSP in a graphics processing subsystem is difficult because the discrete memories require high memory capacity and wide printed circuit board space. Moreover, the data interface between the discrete memories requires more pins than can be implemented in a single VLSI circuit. As a result, there is a desire to allocate the discrete memories into the display memory already present in the graphics processing subsystem and implement the VDSP in a very large scale integrated (VLSI) circuit.
However, the bandwidth required by the combined memories is prohibitively high. For example, the FAROUDJA VP250/LD200 VDSP system manufactured by FAROUDJA LABORATORIES of Sunnyvale, Calif., requires five discrete field memories and 17 discrete line memories. The total capacity of these memories is approximately 1.3 megabytes (MB). Since each memory has a read port and a write port, there are 44 total input and output ports and the total memory data interface bus is 208 bits in this example. In addition, the operating clock frequency is 13.5 Megahertz (MHz) for the five field memories and 13 line memories and 27 MHz for four line memories. Accordingly, the total memory bandwidth is 715 MB/second. This bandwidth exceeds the maximum speed of the graphics processing subsystem display memory.
Accordingly, there is a need for a way to replace the multiple discrete memories required by the VDSP with a local internal memory and an external general purpose memory while reducing the total required bandwidth to achievable levels. The local internal memory would be located within the VDSP for performance reasons and the external general purpose memory would be incorporated into the inexpensive, fast, external display memory already present in the graphics processing subsystem.